8051 Interrupt Structure

8051 Interrupt Structure

AU : June-07, Dec,-07, 12, 14, 16, May-11, 13, 16

The 8051 provides 5 interrupt sources. The 8052 provides 6. These are shown in Fig. 16.7.1. The external Interrupts  can each be either level-activated or transition-activated, depending on bits ITO and IT1 in Register TCON. The flags that actually generate these interrupts are bits IE0 and IE1 in TCON. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. If the interrupt was level-activated, then the external requesting source is what controls the request flag, rather that the on-chip hardware.

The Timer 0 and Timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except see Timer 0 in Mode 3).

The timer flag set upon generation of interrupt is cleared by the on-chip hardware when microcontroller starts execution of particular interrupt service routine.

The serial port interrupt is generated by the logical OR of RI and TI. Neither of these flags is cleared by hardware when the service routine is vectored to service routine. In fact, the service routine will normally have to determine whether it was RI or TI that generated the interrupt and the bit will have to be cleared in software.

1. Interrupt Control (Enabling and Disabling Interrupts using IE)

When 8051 is reset, all interrupts are disable. These are enabled by software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software.

Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE (Fig. 16.7.2). IE contains also a global disable bit, EA, which disables all interrupts at once.

Note in Fig. 16.7.2 that bit position IE.6 is unimplemented. In the 8051s, bit position IE.5 is also unimplemented. User software should not write Is to these bit positions, since they may be used in future MCS-51 products.

Example 16.7.1 Write a program to enable serial interrupt, Timer 1 interrupt and external hardware interrupt 0 (EX0)

Solution :

MOV IE, #1001 1001B ; enable serial, Timer 1, EX0

Example 16.7.2 Write an instruction to disable all interrupts. 

Solution : By making EA = 0 we can disable all interrupts.

CLR IE.7 ; Clear EA bit in the IE register

Example 16.7.3 Write a program to enable Timer 0 interrupt using manipulation instructions.

Solution :

SETB          IE.7   ; Enable interrupts

SETB          IE.1   ; Enable timer 0 interrupt

2. Interrupt Priority and Interrupt Destinations (Vector Locations)

Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IP (Fig. 16.7.3). A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt can't be interrupted by any other interrupt source.

If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced.

Thus within each priority level there is a second priority structure determined by the polling sequence, as follows :

Note that the "priority within level" structure is only used to resolve simultaneous requests of the same priority level.

Review Questions

1. Explain the register IE format of 8051.

2. Explain the interrupt structure of 8051 microcontroller and explain how interrupts are prioritized.

AU : June-07, Dec.-07, Marks 8

3. Explain the interrupt structure with the associated registers in 8051 microcontroller. AU : May-11, Dec.-12, Marks 8

4. Explain the vectored interrupts in 8051 microcontroller. AU : May-13, Marks 8

5. Explain interrupt structure of 8051 in detail. AU : Dec.-14, 16, Marks 16

6. Explain the vectored interrupts in 8051 microcontroller. AU : May-16, Marks 8