Biasing of MOSFET

Biasing of MOSFET

• Common-source circuit is one of the basic MOSFET circuit configurations. The Fig. 4.5.1(a) shows the n-channel enhancement-mode MOSFET circuit with the source terminal is at ground potential and is common to both the input and output sides of the circuit.

 • It is important to note that the coupling capacitor Cc acts as an open circuit to d.c. but it allows the signal voltage to be coupled to the gate of the MOSFET.

• The d.c. equivalent circuit is shown in Fig. 4.5.1 (b).

• Since the gate current into the MOSFET is zero, the voltage at the gate is given by a voltage divider, which can be written as,

• Assuming that the gate-to-source voltage given by equation (4.5.1) is greater than VT and MOSFET is biased in the saturation region, the drain current is,

I_D = K(V_GS – V_T)² … (4.5.2)

• Note that, capital notations for voltage and current indicate d.c. values.

• Applying KVL to drain circuit we have,

V_DS = V_DD - I_D R_D

• If V_DS > V_DS(sat) = V_GS - V_T, then the MOSFET is biased in the saturation region, as we initially assumed, and our analysis is correct. If V_DS < V_DS(sat) then the MOSFET is biased in the nonsaturation region, and the drain current is given by,

I_D = K [2(V_GS – V_T) V_DS V²_GS ]

 

Ex. 4.5.1 For the circuit shown in Fig. 4.5.1 (b), assume that R₁ = 30 kΩ, R₂ = 10 kΩ, RD = 40 kΩ, V_DD = 10 V, V_T = 1V V_GS = 2V K = 0.1mA/v2. Find  I_D and V_DS.

Sol. :

Step 1 : Calculate V_G

From the circuit shown in Fig. 4.5.2 and equation (4.5.1), we have,

Step 2 : Calculate l_D

Assuming the MOSFET is biased in the saturation region, the drain current is,

I_D = K(V_GS –V_T)² = (0.1) (2-1)² =  0.1mA

Step 3 : Calculate V_DS

V_DS = V_DD - I_D R_D = 10 - (0.1) (40) = 6 V

Validity of assumption : Because

V_DS = 6 V > V_DS(sat) = VGS - VT = 2 - 1 = 1V, the MOSFET is indeed biased in the saturation region and our calculations are valid.

 

Ex. 4.5.2 Calculate the D.C. operating condition for the circuit diagram shown in Fig. 4.5.3.

Assuming transistor is biased in the saturation, the drain current is

Comment : Because V_DS = 8.65 V > V_DS(sat) = V_GS - V_T = 4 - 1 = 3, the transistor is indeed biased in the saturation region and our analysis is valid.

Biasing circuit for p-channel enhancement-mode MOSFET

• Fig. 4.5.4 shows a common-source circuit with a p-channel enhancement-mode MOSFET.

• Here, the source is tied to +VDD/ which become signal ground in the a.c. equivalent circuit. Thus it is also a common-source circuit.

• The d.c. analysis for this circuit is essentially the same as for the n-channel MOSFET circuit. The gate voltage is given by,

V_G = (R₂ / R₁ R₂)(V_DD) ….(4.5.4(a))

and the source-to-gate voltage is given by,

V_SG = V_DD -V_G     ….  (4-5.4 (b))

• Assuming that V_GS < V_T , or V_SG > |V_T |, and that the device is biased in the saturation region, the drain current is given by,

I_D- K(V_SG + V_T)2  ...(4.5.5)

and the source-to-drain voltage is,

V_SD = V_DD - I_DR_D

• If V_SD > V_SD(sat) = V_SG + V_T   the MOSFET is indeed biased in the saturation region, as we have assumed. However, if V_SD < V_SD(sat) the MOSFET is biased in the nonsaturation region.

 

Ex. 4.5.3 Calculate the drain current and source to drain voltage of a common source circuit, shown in the Fig. 4.5.5. Also verify the region of operation. Device parameters V_T = - 0.8 V and k = 0.2 mAJV².

Sol. :

Since | V_GS | > | V_T | it is the nonlinear region of operation.

 

Ex. 4.5.4 Consider the circuit shown in Fig. 4.5.6. Assume that, R1 = 20 kΩ, R2 = 60 kΩ, VDD = 10 V, RD=15kΩ, VT=-0SV, and K = 0.2 mA/v2. Find I_D and V_SD

Sol. : From the circuit shown in Fig. 4.5.6 we have,

The source-to-gate voltage is therefore,

V_SG = V_DD – V_G = 10 -7.5 = 2.5 V

Assuming the MOSFET is biased in the saturation region, the drain current is,

I_D = K(V_SG + V_T)²

= (0.2) (2.5 -0.8)² = 0.578 mA

and the source-to-drain voltage is

V_SD = V_DD I_DR_D

= 10 – (0.578) (15) = 1.33 V

• Since V_SD = 1.33 V is not greater than V_SD(sat) = V_SG + V_T = 2.5 - 0.8 = 1.7 V, the p-channel MOSFET is not biased in the saturation region, as we initially assumed.

Calculate I_D for nonsaturation region

• In the nonsaturation region, the drain current is given by,

I_D = K[2(V_SG + V_T)V_SD –V²_SD]

and the source-to-drain voltage is

V_SD = V_SD  - I_D R_D

Combining these two equation, we obtain

I_D = K[2(V_SG + V_T)(V_DD -  I_DR_D) (V_DD -  I_DR_D)²]

For simplicity, we take resistance values in k Ω  so we get value of I_D in mA.

• To bias MOSFET in non-saturation region V_SD < V_SD(sat) the V_SD = L48 V satisfies this condition and hence I_D = 0.568 mA is valid. Thus,

I_D = 0.568 mA and V_SD = 1.48 V

 

1. Load Line and Modes of Operation

• The load line gives a graphical picture by which we can visualize the region in which the MOSFET is biased.

• Consider the common-source circuit shown in Fig. 4.5.7 (a).

• Writing Kirchhoff's voltage law around the drain-source loop results V_DS = V_DD - I_DR_D, which is the load line equation.

• It shows a linear relationship between the drain current and drain-to-source voltage.

• Fig. 4.5.7 (b) shows the VDS(sat) characteristic for the MOSFET described in example 4.5.1.

• The load line is given by

and is also plotted in the figure. The two end points of the load line are determine in the usual manner. If the drain current = 0, then VDS= 10 V; VDS " 0, then drain current = 10/40 = 0.25 mA.

• The Q-point of the MOSFET is given by the d.c. drain current (ID) and drain-to-source voltage (VDS) and it is always on the load line, as shown in the Fig. 4.5.7 (b).

• If the gate-to-source voltage is less than VT, the drain current is zero and the MOSFET is in cut-off.

• As the gate-to-source voltage becomes just greater than the threshold voltage, the MOSFET turns ON and is biased in the saturation region.

• As V_GS increases, the Q-point moves upon the load line.

• The transition point is the boundary between the saturation and non-saturation regions. It is the point where,

• V_DS = V_DS(sat) = V_GS - V_T . AS V_GS increases further, the MOSFET operates in nonsaturation region.

 

Ex. 4.5.5 Consider the circuit shown in Fig. 4.5.7 (a). Assume V_T = 1V and

K = 0.1mA/v². Determine the transition parameters for the given circuit.

Sol. : At the transition point,

• For VGS < 2.461 V the MOSFET is biased in the saturation region and for VGS > 2.461 V, the MOSFET is biased in the nonsaturation region.

Summary of step in the d.c. analysis of MOSFET circuits

• To analyze the d.c. response of a MOSFET circuit we require to know the bias condition (saturation or non-saturation) of the MOSFET. In some cases, the bias condition is not given, which means that we have to assume any one bias condition, then analyze the circuit to determine if the solution consistent with our initial assumption. To do this, we have to perform following steps.

1. Assume that, the MOSFET is biased in the saturation region, in which case VGS > V_T, I_D > 0 and V_DS ≥ V_Ds(sat)

 2. Analyze the circuit using the saturation current-voltage relations.

3. Evaluate the resulting bias condition of the MOSFET. If the assumed parameter values in step-1 are valid, then the initial assumption is correct. If V_GS < V_T, then the MOSFET is probably cut-off, and if V_DS < _VDS(sat), the MOSFET is likely biased in the non-saturation region.

4. If the initial assumption is proved incorrect, then a new assumption must be made and the circuit must be reanalyzed.

 

2. Common MOSFET Configurations : D.C. Analysis

• There are various other MOSFET circuit configurations. Let us analyze and design them one by one.

a. CS Circuit with Source Resistor

Voltage divider bias :

• Fig. 4.5.9 shows common source circuit with source resistor for n-channel enhancement type MOSFET.

As I_G = 0A

V_G = R₂ V_DD / R₁ + R₂  … (4.5.5)

Applying KVL to output circuit we get,

Ex. 4.5.6 For the circuit shown in Fig. 4.5.10. Calculate V_G, I_D, and V_DS.

Sol :

Step 1 : Calculate V_G

Step 2 : Obtain expression for V_GS

Step 3 : Calculate K

Step 4 : Obtain the value of I_DQ

Assuming that the gate to source voltage is greater than V_T and transistor is biased in the saturation region.

We have,     I_D = K(V_GS - V_T )²

Substituting value of V_GS we get,

 

 

Ex. 4.5.7 Determine I_DQ, V_GSQ, V_D and V_S for the MOSFET circuit shown in Fig. 4.5.11. Given for MOSFET, V_GS(+h) = 3 V, I_D(ON) = 5 mA, V_GS(ON) = 6 v.

Sol :

 

Ex. 4.5.8 For the d.c. circuit in Fig. 4.5.12 assume the MOSFET parameters are VT =2 V, k' = 80 µA/V2 and W/L = 4. Choose R1 and R2 such that the current in the bias resistors is approximately one-tenth of ID. Design the circuit such that ID = 0.5 mA. Use standard resistor values.

 

Sol. : Assuming the MOSFET is biased saturation region, we have,

The current through the bias resistor should be approximately

The closest standard resistor values are R₂ =120 kΩ and R₁ = 300 kΩ

Validity of assumption :

Therefore, the MOSFET is biased in the saturation region, as initially assumed.

Important Concept

There are certain tolerances in resistor values as well as tolerances in MOSFET conduction parameter and threshold voltage values. These tolerances lead to variations in the Q-point values. Thus, Q-point should not be designed too close to the transition point to avoid Q-point to enter into nonsaturation region because of parameter variations. In bipolar circuits, we have seen that the Q-point tended to be stabilized when an emitter resistor was included in the circuit. In a similar way, the Q-point of MOSFET circuits will tend to be stabilized against variations in transistor parameters by including a source resistor. 

 

Ex. 4.5.9 Determine the d.c. bias point for the EMOSFET circuit in Fig. 4.5.13. Assume k = 0.4 mA/V², V_T = 3 V.

 

Sol. : The Fig. 4.5.13 (a) shows the equivalent circuit

 

 

Ex. 4.5.10 For the E-MOSFET ci rcuit shown in Fig. 4.5.14, V_DS = 1/2 V_DD and I_D = I_D(ON). Determine V_DD, R_D and V_GS For MOSFET, V_GS(ON) = 6V, I_D(ON) = 4 mA and V_GS(+h) = 3 V.