Microprocessors and Microcontrollers: Unit IV: (a) Programmable Peripheral Interface (PPI) - 8255
Block Diagram
Programmable Peripheral Interface (PPI) - 8255
Fig. 8.3.1 shows the internal block diagram of 8255A. It consists of data bus buffer, control logic and Group A and Group B controls.
Block Diagram
AU
: May-06, 09, 13, 14, 18, Dec.-13, 15, 17
Fig.
8.3.1 shows the internal block diagram of 8255A. It consists of data bus
buffer, control logic and Group A and Group B controls.
1. Data Bus Buffer
This
tri-state bi-directional buffer is used to interface the internal data bus of
8255 to the system data bus. Input or Output instructions executed by the CPU
either Read data from, or Write data into the buffer. Output data from the CPU
to the ports or control register, and input data to the CPU from the ports or
status register are all passed through the buffer.
2. Control Logic
The
control logic block accepts control bus signals as well as inputs from the
address bus, and issues commands to the individual group control blocks (Group
A control and Group B control). It issues appropriate enabling signals to
access the required data/control words or status word. The input pins for the
control logic section are described here.
3. Group A and Group B Controls
Each
of the Group A and Group B control blocks receives control words from the CPU
and issues appropriate commands to the ports associated with it. The Group A
control block controls Port A and PC7-PC4 while the Group
B control block controls Port B and PC3 - PC0.
Port
A :
This has an 8-bit latched and buffered output and an 8-bit input latch. It can
be programmed in three modes: mode 0, mode 1 and mode 2.
Port
B :
This has an 8-bit data I/O latch/buffer and an 8-bit data input buffer. It can
be programmed in mode 0 and mode 1.
Port
C :
This has one 8-bit unlatched input buffer and an 8-bit output latch/buffer.
Port C can be separated into two parts and each can be used as control signals
for ports A and B in the handshake mode. It can be programmed for bit set/reset
operation.
Review Questions
1. Draw and explain
the block diagram / architecture of 8255.
AU: May-06, 09, Marks
12
2. Draw and explain
the functional block diagram of 8255 PPI.
AU: Dec.-13, May-13,
14 Marks 10
3. Explain the
architecture, functions and registers of the 8255 PPI.
AU: Dec.-15, Marks 8
4. Draw the block
diagram of 8255 (PPI).
AU: Dec.-17, Marks 13
5. Draw the functional
diagram of 8255.
AU: May-18, Marks 4
Microprocessors and Microcontrollers: Unit IV: (a) Programmable Peripheral Interface (PPI) - 8255 : Tag: : Programmable Peripheral Interface (PPI) - 8255 - Block Diagram