CPLD (Complex Programmable Logic Devices)

CPLD (Complex Programmable Logic Devices)

Simple PLDs (SPLDs) include PLAs, PALs and other similar types of devices.

• SPLDs have limitations of number of input product terms and outputs. For applications which requires more number of inputs or product terms or output we have to expand the capacity of PLDs by cascading them.

• The Complex Programmable Logic Devices (CPLDs) are introduced to solve the above mentioned difficulty of SPLDs. A typical CPLD is merely a collection of multiple PLDs and an interconnection structure, all on the same chip, as shown in the Fig. 9.6.1.

• In CPLDs, in addition to the individual PLDs the on-chip interconnection structure is also programmable. Therefore, unlike PLDs, the CPLDs can be scaled to larger sizes by increasing the number of individual PLDs.

1. Block Diagram

• The Fig. 9.6.2 shows the block diagram of a Complex Programmable Logic Device (CPLD).

• It consists of collection of PAL like blocks, I/O blocks and a set of interconnection wires, called programmable interconnection structure.

• The PAL like blocks are connected to the programmable interconnect structure and to the I/O blocks. The chip input-output pins are attached to the I/O blocks.

• A PAL like block in the CPLD usually consists of about 16 macrocells. Like other macrocells, the macrocell in CPLD consists of AND-OR configuration, an EX-OR gate, a flip-flop, a multiplexer, and a tri-state buffer.

• The Fig. 9.6.3 shows the typical macrocell for CPLD. Each AND-OR configuration usually consists of 5-20 AND gates and an OR gate with 5-20 inputs.

• The EX-OR gate provides the output of OR-gate in inverted or non-inverted form as per the fuse link status.

• AD flip-flop stores the output of EX-OR gate.

• A multiplexer selects either the output of the D flip-flop or the output of the EX-OR gate depending upon its select input (either 1 or 0).

• The tri-state buffer acts as a switch which enables or disables the output.

2. Architecture of XC9572 CPLD

• The XC9572 is a device from XC9500 CPLD family. It consists of 4 functional blocks (FBs), 72 macrocells, 1600 usable gates and 72 registers. The XC9572 device is available in several different packages. Different I/O packages have different number of I/O pins. For example, 44-pin PLCC has 34 I/O pins and 100-pin TQFP has 72 I/O pins.

• In XC9572, the functional blocks and I/O blocks are fully interconnected by the FastCONNECT switch matrix. The IOB provides buffering for device inputs and outputs. Each FB provides programmable logic capacity with 36 inputs and 18 outputs. The Fast CONNECT switch matrix connects all FB outputs and input signals to the FB inputs. For each FB, 12 to 18 outputs (depending on package pin-count) and associated output enable signals drive directly to the IOBs. This is illustrated in Fig. 9.6.4.

Review Questions

1. State the limitation of SPED.

2. Draw and explain the general architecture of CPLD.

3. What it meant by CPLD ? Draw and explain the block diagram of CPLD.

4. Explain the architectural features ofXC9572.

5. Draw the basic structure of CPLD. Explain its features in brief.