Interrupt Sequence with 8085

Interrupt Sequence with 8085

The events occur as follows in an 8085 system :

1. One or more of the INTERRUPT REQUEST lines (IR₀-IR₇) are raised high, setting the corresponding IRR bit(s).

2. The priority resolver checks three registers : The IRR for interrupt requests, the IMR for masking bits, and the ISR for the interrupt request being served. It resolves the priority and sets the INT high when it is appropriate to do so.

3. In response to the INTR signal, 8085 completes current instruction cycle and executes interrupt acknowledge cycle, thus giving an pulse.

4. Upon receiving an  from the 8085, the highest priority ISR bit is set and the corresponding IRR bit is reset. Then 8259A places the opcode for CALL instruction on the data bus.

5. This CALL instruction initiates two more interrupt acknowledge cycles.

6. These two interrupt acknowledge cycles allow the 8259 to release preprogrammed subroutine address onto the data bus. In response to second interrupt acknowledge pulse, 8259 places a lower byte of interrupt subroutine address and in response to third interrupt acknowledge pulse 8259 places a higher byte of the subroutine address.

7. This completes the interrupt cycle. In the AEOI (Automatic End of Interrupt) mode the ISR bit is reset at the end of the second  pulse. Otherwise, the ISR bit remains set until the issue of an appropriate EOI command at the end of the interrupt subroutine.

Review Question

1. Explain the processing of interrupt using 8259.