Parallel Communication between Two MP Kits using Mode 2 of 8255

Parallel Communication between Two MP Kits using Mode 2 of 8255

AU : May-05

The Fig. 8.8.1 shows a block diagram to implement the bidirectional communication between the master and the slave processors. As shown in the Fig. 11.28, the data buses of two processors are interconnected through the 8255, which servers as a peripheral device of the master processor. Here, 8255 is used in bidirectional I/O mode (mode 2), in which port A of the 8255 is used for bidirectional data transfer, and four signals from port C are used for handshaking.

Transfer of data from master processor to slave processor

1. The master processor reads the status of  to verify whether the previous byte has been read by the slave processor.

2. If master processor finds output buffer empty it writes data into port A and informs slave processor by activating the  signal.

3. The slave processor checks the  signal from the master processor for the presence of data.

4. If it finds active  signal, it reads data from port A and acknowledges the reading at the same time by activating the  signal.

Transfer of data from slave processor to master processor

1. The slave processor checks the IBF (input buffer full) signal from 8255 to find out whether port A is available (empty) to transfer a data byte.

2. If slave processor confirms availability of port A it sends a data byte on the data bus and informs the 8255 by activating  signal.

3. Since the data is loaded in the 8255 its IBF signal is activated and master processor reads this signal to check the presence of data.

4. If master processor finds IBF signal activated it reads the data byte from port A.

Review Question

1. Explain the parallel communication between two processors using mode 2 of 8255.