Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits

Analysis & Design of Synchronous Sequential Circuits

Digital Logic Circuits

Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits : Syllabus, Contents

UNIT - III

 Chapter – 5

(b) Analysis & Design of Synchronous Sequential Circuits

 

Syllabus

Counters - Asynchronous and synchronous type - Modulo counters. Design of synchronous sequential circuits - Moore and Melay models - Counters, State diagram ; State reduction; State assignment. 

Contents

5.1 Introduction …. 5-2  …. May-06, Marks 4

5.2 Clocked Sequential Circuits        ….. 5-2  May-05, 09, 17, Dec.-08, 11, Marks 4

5.3 Analysis of Clocked Sequential Circuits        …… 5-6 May-07, 12, Dec.-03, 06, 07, 15, Marks 16

5.4 Design of Clock Sequential Circuits ….. 5-12 … May-07, 08, 10, 13, 15, 16, June-09, Dec 03, 05, 06, 07, 12 Marks 16

5.5 Counters ….. 5-46 …. Dec.-08, Marks 2

5.6 Ripple / Asynchronous Counters         …… 5-47 ….. May-03, Dec.-09, 14, Marks 16

5.7 Design of Ripple (Asynchronous) Counters . . ..5 – 56 …. Dec.-04, May-06, 09, 10, 11, Marks 16

5.8 Synchronous Counters …. 5-58 …. Dec.-06, May-08, Marks 8

5.9 Design of Synchronous Counters         …. 5-62 ….. Dec.-03, 07, 08, 09, 10, 11, 12, 15, 16, May-03, 04, 05, 08, 09, 11, 15, Marks16

5.10 ….. Sequence Detector ….. 5-79

Dec.-12, 15, 16, Marks 13

5.11 Two Marks Questions with Answers …. 5-91

5.12 University Questions with Answers

(Long Answered Questions) ….. 5-92


Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits : Tag: : Digital Logic Circuits - Analysis & Design of Synchronous Sequential Circuits