Digital Logic Circuits: Unit II: Combinational Circuits : Syllabus, Contents
UNIT – II
Chapter – 3
Combinational Circuits
Syllabus
Combinational
logic - Representation of Logic Functions – SOP and POS forms, K-map
representations – Minimization using K maps – Simplification and implementation
of combinational logic – Multiplexers and demultiplexers – code converters,
Adders, Subtractors, Encoders and Decoders.
Contents
3.1
Review of Boolean Algebra 3-2
Dec.-05,
07, 08, 11, May-03, 04, 05. 08, 10, 15. Marks 8
3.2
Representation of Logic Functions - SOP and POS Forms …. 3-6
Dec.-03,
12, May-15, Marks 8
3.3
Karnaugh Map (K-map) Representation and Minimization using K-maps ….. 3-13
3.4
Minimization of SOP Expressions …. 3-22
Dec.-03,
05, 17, May-05, 06, 10, 13, Marks 12
3.5
Minimization of POS Expressions …..
3-31
May-04,
May-15, Marks 8
3.6
Five-Variable K-map …... 3-34
May-05,
06, 09, 12, 13, Dec.-04, 05, 06, 08, 11, 12, Marks 10
3.7
Six-Variable K-map ….. 3-38
3.8
Limitations of K-maps …. 3-41
3.9
Implementation of Logic Functionsusing Logic Gates …. 3-41
3.10
Introduction to Combinational Logic Circuit 3 - 58
Dec.-07,
08, Marks 8
3.11
Adders ….. 3-60
Nov.-10,
May-15, 16 Marks 8
3.12
Subtractors ……. 3-62
Dec-14,
15, 16, Marks 13
3.13
Parallel Adder …… 3-65
May-12,
Marks 8
3.14
Parallel Adder …. 3-65
Dec-12,
Marks -8
3.15
Parallel Adder / Subtractor …. 3-66
3.16
BCD Adder …. 3-67
Dec-7,
Marks -6
3.17
Multiplexers …. 3-69
3.18
Demultiplexers …. 3-81
3.19
Decoder ….. 3-86
Dec.-06,
08, 13, May-07, 11, 17, Marks 16
3.20 Encoder …. 3-96
3.21 Code Converters ….. 3-99
Dec.-03,
11, 14, 15, 16, May-10, 11, 15, 16 June-09, Marks 16
3.22 Two Marks Questions with Answers 3 -105
3.23 University Questions with Answers
(Long Answered Questions) 3 -112
Digital Logic Circuits: Unit II: Combinational Circuits : Tag: : Digital Logic Circuits - Combinational Circuits
Digital Logic Circuits
EE3302 3rd Semester EEE Dept | 2021 Regulation | 3rd Semester EEE Dept 2021 Regulation