Examples of Procedure and Functions

Examples of Procedure and Functions

Ex. 10.13.1 : Behavioural description of a full adder using procedure and task.

We have seen the structural description of full-adder using two half-adders. Here, we see the behavioral description of half-adder using the procedure in VHDL. The Fig. 3.11.9 shows the block diagram of a full-adder using two half-adders and the OR-gate and the listing 10.13.1 shows the HDL description for the full adder.

Listing 10.13.1 : VHDL description of a full adder using procedure.

library ieee;

use ieee.std_logic_1164.all;

entity full_adder is

port ( A, B. Cin : in std_logic;

Sum, Cout: out std_logic);

end full_adder;

architecture two_h_adders of full_adder is

procedure H_Addr ( S, C : out std_logic;

a, b : in std_logic) is - procedure half adder

begin

S : = a xor b;

C := a and b;

end H_Addr;

begin

addfull: process (A, B, Cin)

variable Suml, Sum2, Cl, C2, temp: std_logic;

begin

H_Addr (Suml, Cl, A, B); -  First call to procedure Half Adder

H_Addr (Sum2, C2, Suml, Cin); - Second call to procedure Half Adder

temp := Cl or C2;

Sum <= Sum2;

Cout <= temp;

end process;

end two_h_adders;

 

Ex. 10.13.2 : Behavioural description of an N-bit ripple carry adder using procedure and task.

Here, we see the VHDL behavioural description of N-bit full adder using procedure.

Listing 10.13.2 : VHDL description of an N-bit ripple carry adder using procedure,

library ieee;

use ieee.std_logic_1164.all;

entity adder is

generic (N : integer := 4);

port ( A, B : in std_logic_vector (N downto 0);

Cin : in std_logic;

Sum : out std_logic_vector (N downto 0);

Cout : out std_logic);

end adder;

architecture adder_ripple of adder is

procedure full_addr ( S, C : out std_logic;

a, b, cin : in std_logic) is -procedure full adder

begin

S := a xor b xor cin;

C : = (a and b) or (a and cin) or (b and cin);

end full_addr;

begin

ri_addr: process (A, B, Cin)

variable cl, c2, teml, tem2 : std_logic;

variable carry : std_logic_vector (N+l downto 0);

variable suml : std_logic_vector (N downto 0);

begin

carry(O) := Cin;

for i in 0 to N loop

full_adder (suml(i), carry(i+l), A(i), B(i), carry(i));

- calls procedure full_addr

end loop;

Sum <= suml;

Cout <= carry(N-l-l);

end process;

end adder_ripple;

 

Ex. 10.13.3 : Function to calculate a XOR b.

Listing 10.13.3 shows the use of function to calculate a XOR b.

Listing 10.13.3

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Func_XOR is

port ( al, bl : in std_logic;

yl : out std_logic);

end Func_XOR;

architecture Behavioral of Func_XOR is

function exor (a, b : in std_logic) return std_logic is

variable y : stdlogic;

begin

y : = a xor b;

return y;

end function exor;

begin

process (al, bl)

begin

yl <= exor (al, bl); - function call

end process;

end Behavioral;

Review Question

1. Explain functions and subprograms with suitable examples.