Declaration of Subprogram

Declaration of Subprogram

• VHDL distinguishes between a subprogram declaration and a corresponding subprogram body. The subprogram declaration contains only interface information, while the subprogram body contains :

- Interface information

- Local declarations

- Statements

• Subprograms may be declared / defined in any declarative part of a VHDL object. The actual definition of the behaviour may also be separated from the declaration, which is often the case when packages are split into package and package body. In such cases, the subprogram body may be described possibly in a package body and then, in the package declaration, the corresponding subprogram declaration is specified. The subprogram which is declared in a package may be used in all unit that reference this package. The syntax for subprogram declaration is :

subprogram-specification;

Examples of subprogram declaration are :

procedure calculate (A, B, C : in INTEGER;

OP : in OP_CODE;

Z : out INTEGER;

function add (a, b : in INTEGER) return INTEGER;

Review Question

1. Write a note on declaration of subprogram.