Instruction Cycle, Machine Cycle and T-State

Instruction Cycle, Machine Cycle and T-State

AU : May -08, Dec . – 09

During normal operation, the microprocessor sequentially fetches, decodes and executes one instruction after another until a halt instruction (HLT) is executed. The fetching, decoding and execution of a single instruction constitutes an instruction cycle, which consists of one to five read or write operations between processor and memory or input/output devices. Each memory or I/O operation requires a particular time period, called machine cycle. In other words, to move byte of data in or out of the microprocessor, a machine cycle is required. Each machine cycle consists of 3 to 6 clock periods/cycles, referred to as T-states. Therefore we can say that, one instruction cycle consists of one to five machine cycles and one machine cycle consists of three to six T- states i.e. three to six clock periods, as shown in the Fig. 5.1.1.

There are seven different types of machine cycles in the 8085A. Three status signals  , S₁ and S₀ identify each type as shown in Table 5.1.1. These signals are generated at the beginning of each machine cycle and remain valid for the duration of the cycle.

Review Question

1. Distinguish between an instruction cycle, a machine cycle and a clock  with an example instruction.

AU : Dec-09, Marks 6