Memory Description in VHDL

Memory Description in VHDL

• Memory is nothing but the array of registers. Each register in the array is identified by its unique address. The number of bits in each register decides the word length. Thus, in VHDL we can model memory using two dimensional array which implements an array of registers.

Read and Write Memory Operation

• The example 10.17.1 illustrates the read and write operation of memory. The memory used in this example has 1024 words of 8-bit each (IK × 8 memory). There are 10 address bits (since 2¹⁰ = 1024).

• There are two control inputs : Enable and Read Write.

• There are two data lines : Dataln and DataOut; each have 8-bits.

• A memory operation is enabled only when Enable input is active (logic 1). Read and Write operations are performed as shown below :

Read Operation :          Dataout ← Memory [A]

Enable = 1 and ReadWrite = 1

Write operation : Memory [A] ← Dataln;

Enable = 1 and ReadWrite = 0

• When Enable is 0, the memory is disabled and the outputs are in high impedance state (z).

Ex. 10.18.1 Write an VHDL code that illustrates the read and write operations of memory.

library ieee;

use ieee.std_logic_1164.all;

package array_2D is

constant N : integer := 1023; - N + 1 is the number of elements in the array,

constant L : integer := 7;          - M + 1 is the number of bits of each element of the array,

subtype Ele_width is std_logic_vector (M downto 0);

type Ele is array (N downto 0) of Ele_width;

end array_2D;

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use work.array_2D.all;

entity meml024x8 is

generic ( N : integer := 1023;

L : integer : = 7); - N + 1 is the number of words in the memory

- M + 1 is the number of bits of each word.

Port ( Memory : inout Ele;

Enable : in std_logic;

Address : in unsigned (9 downto 0); — To address 1024 words 10_bit address bus

Dataln : in std_logic_vector (7 downto 0);

ReadWrite : in std_logic;

DataOut: out std_logic_vector (7 downto 0));

end meml024x8;

architecture SRAM of meml024x8 is

begin

rd_wr : process (Enable, Address, Dataln, ReadWrite)

variable A : integer range 0 to 1023;

begin

if (Enable = '0') then

A := To_Integer (Address); — To_Integer is a built-in function

if (ReadWrite = '0') then

Memory (A) < = Dataln;

else

DataOut <= Memory (A);

end if;

else

DataOut < = "ZZZZZZZZ"; - Make D_out high impedance.

end if;

end process rd_wr;

end SRAM;

Review Question

1. How is memory modelled in VHDL ? Write a VHDL code that illustrates the read and write operations of memory.