Styles of Modeling

Styles of Modeling

AU : Dec.-14, 15, 16, 17, May-15

• In a VHDL or Verilog program, architecture body (VHDL) or the module (Verilog) contains a series of concurrent statements. All concurrent statements execute simultaneously. HDL has several different concurrent statements. Also, it has a mechanism which bundles a set of sequential statements which operate as a single concurrent statement. The way in which these statements are used is called the modeling style or types of descriptions. Thus these statements give rise to six different modeling styles or types of descriptions as,

* Behavioral

* Data flow

* Structural

* Switch-level

* Mixed-Type

* Mixed-Language

• Let us see the VHDL description of full adder shown in the Fig. 10.3.1 in various modeling styles.

 

1. Behavioral Description

• It is sometimes possible to directly describe the behavior or the functionality of a circuit. Such a modeling style is called behavioral modeling which is very similar in syntax and semantics to that of a high-level programming language (For example : C, Pascal). A behavioral description models the system as to how the outputs behave with the inputs.

• In VHDL, the behavior of the entity is expressed using sequentially executed, procedural code. The key mechanism used to model the behavior of the entity is, a process statement.

Listing 10.3.1 : Example of VHDL behavioral

description

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit);

end full_add;

architecture adder of full_add is

begin

process (A, B, Cin)

begin

Sum < = A xor B xor Cin;

Cout < = (A and B) or (Cin and A) or (Cin and B);

end process;

end adder;

In Verilog, the key mechanism used to model the behavior is predefined words always or initial.

Listing 10.3.2 : Example of Verilog behavioral

description

module full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

output Sum, Cout;

reg Sum, Cout;

always @(A, B, Cin)

begin

Sum = (A ^Λ B) ^Λ Cin;

Cout = (A & B) | (Cin & A) | (Cin & B);

end

endmodule

 

2. Dataflow Description

• Data flow describes how the circuit signals flow from the inputs to the outputs. There are some concurrent statements which allow to describe the circuit in terms of operations on signals and flow of signals in the circuit. When such concurrent statements are used in a program, the style is called a 'dataflow design'. Concurrent signal assignment statements are used in this type of modeling style.

Listing 10.3.3 : Example of VHDL data-flow

description

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit); end full_add;

architecture adder of full add is

begin

Sum < = A xor B xor Cin;

Cout < = (A and B) or (Cin and A) or (Cin and B);

end adder;

In Verilog, predefined word assign is used to assign a value to the left-hand side of a signal-assignment statement.

Listing 10.3.4 : Example of Verilog data-flow

description

module full_add (A, B, Cin, Cout, Sum);

input A, B, Cin;

output Sum, Cout;

assign Sum = (A ^Λ B) ^Λ Cin;

assign Cout = (A & B) | (Cin & A) | (Cin & B);

endmodule

• The built in operators of VHDL (for example : AND, OR, NOT) and verilog (for example & I A) are used in the expression.

• Here, the data flow model for the full_add is described using a two concurrent signal assignment. In a signal assignment statement, the symbol <= implies an assignment of a value to a signal in VHDL. The value of the expression on the right-hand-side of the statement is computed and is assigned to the signal on the left-hand-side, called a target signal. In Verilog, predefined word assign is used to assign a value to a signal. A concurrent signal assignment is executed only when any signal in the expression on the right-hand-side has an event on it, that is, the value of the signal changes.

 

3. Structural Description

• In structural design, a VHDL and verilog uses components or gates to model the system. The important features of VHDL structural type of architecture body are :

■ Design hierarchy

■ Components are used

■ Each component is simulated separately

• In the structural modeling, an entity is described as a set of components connected by signals, that is, as a netlist. The components used in an architecture may be from a library or may be ones that were previously defined as part of a design.

entity full_add is

port (A, B, Cin : in bit;

Sum, Cout : out bit);

end full_add;

architecture adder of full_add is

component xor3

port ( II, I2,I3 : in bit;

O1 : out bit);

end component;

component and2

port ( I1, I2 : in bit;

O1 : out bit);

end component;

component or3

port ( I1, I2,I3 : in bit;

O1 : out bit);

end component;

signal S1, S2, S3 : bit;

begin

Y1 : xor3 port map (A, B, Cin, Sum);

XI : and2 port map (A, B, SI);

X2 : and2 port map (A, Cin, S2);

X3 : and2 port map (B, Cin, S3);

Y2 : or3 port map (SI, S2, S3, Cout);

end adder;

• The name of the architecture body is adder. The entity declaration for full_add specifies the interface ports for this architecture body. The architecture body is composed of two parts : the declarative part (before the keyword begin) and the statement parts (after the keyword begin). The components may either be predefined components in a library or they may later be bound to other components in a library. The declared components are instantiated in the statement part of the architecture body using component instantiation statement. Yl, XI, X2, X3, Y2 are component labels for this component instantiations. Il is connected to signal A, 12 is connected to signal B, 13 is connected to signal Cin, and O1 is connected to Sum in portmap xor3 gate. Similarly, port maps for and 2 and or 3 are defined. Note that in this case, the signals in the port map of a component instantiation and the port signals in the component declaration are associated by position. A component instantiation statement is a concurrent statement.

Review Questions

1. List the different modeling styles.

2. Explain the behavioral description with example.

3. Explain the dataflow description with example.

4. Explain the structural description with example.

5 Explain the concept of Behavioural modeling and Structural modeling in. VHDL. Take the example of Full Adder design for both and write the coding.

AU : Dec.-14, 15, Marks 16

6. Write a VHDL program for full adder using structural modelling.

7. Explain in detail the concept of structural modeling in VHDL with an example of full adder.

AU : Dec.-16, Marks 13