Digital Logic Circuits: Unit V: VHDL

Subprogram Overloading

VHDL

• It is possible to define two or more different subprograms having the same name but differing in number or type of parameters.

Subprogram Overloading

• It is possible to define two or more different subprograms having the same name but differing in number or type of parameters. The function is said to be overloaded in this case. The simulator or synthesizer automatically selects the correct subprogram by looking at the parameters in the call statement. Overloading is a very convenient mechanism for defining a set of functions that perform the same operation on different data types.

• Let us consider following two declarations :

function add (a, b : INTEGER) return INTEGER;

function add (x, y : BIT) return BIT;

• The above two function are overloaded since they have the same name but different type of parameters

function largest (Nl, N2, N3 : INTEGER) return INTEGER;

function largest (Nl, N2, N3, N4 : INTEGER) return INTEGER;

• The above two functions are overloaded since they have the same name but different number of parameters.

Review Question

1. What do you mean by subprogram overloading ? 


Digital Logic Circuits: Unit V: VHDL : Tag: : VHDL - Subprogram Overloading