Digital Logic Circuits: Unit V: VHDL

Subprograms

Functions, Procedure, Suitable Example | VHDL

• A subprogram defines a sequential algorithm that performs particular task. Two types of subprograms are used in VHDL : Procedures and functions.

Subprograms

• A subprogram defines a sequential algorithm that performs particular task. Two types of subprograms are used in VHDL : Procedures and functions. Procedures and functions in VHDL, are directly analogous to functions and procedures in a high-level programming language such as C or Pascal.

• They provide the ability to execute common routines from several different places in a description. They also provide a means of breaking up large programs into smaller ones to make it easier to read and debug the source descriptions.

Function : Function performs sequential computations and return a value as a the value of the function.

1. Must have at least one input argument.

2. Computes and returns a single value.

3. Executes in zero simulation time.

4. Always terminated by return statement.

5. Can be called only from within process.

Procedure : Procedure performs sequential computations and return values in global objects or by storing values into formal parameters.

1. May be used to partition large behavioral descriptions.

2. May return zero or more values.

3. May or may not execute in zero simulation time, depending on whether it has a wait statement or not.

4. Can be called only from within process.

5. Can have more than one input and output.

• Subprograms written in VHDL must have body and may have declaration. The typical format for a subprogram body is :

subprogram-specification is

subprogram-item-declarations

begin

Subprogram statements

end [function / procedure] [subprogram_name[;

• Subprogram specification gives name of subprogram and it defines the formal parameters, their class (i.e., signal, variable, file or constant), their type, and their mode (in, out or inout).

• When parameters are of a variable or constant class, values are passed to the subprogram by value. On the other hand, files and signals are passed by reference.

• The subroutine-item-declaration contains a set of declaration (e.g., type and object declarations) that are accessible for use within the subprogram. Every time, when subprogram is called, declarations come into effect - variables are created and initialized. Their existence is within the subprogram.

• The subprogram-statement contains sequential statements. These sequential statements define the computation to be performed by the subprogram.

• The subprograms are terminated by return statement. The format of a return statement is :

return [expression];

• The value of the expression in the return statement is returned to the calling program. 

 

1. Functions

• The functions in VHDL have two parts the declaration and the body. The following listing gives the example of function. The declaration of function includes the name of the function, the inputs to the function and their types, and the type of the return data type. The general syntax of function body is

[pure I impure] function function-name (parameter list)

return return type

• The pure and impure are keywords and are optional. They specify whether the function is pure or impure. The function that returns the same value each time when it is called with the same set of actuals is called pure function. By default, the function is pure. The function that returns different values each time it is called with the same set of actuals is called impure function.

• The parameter list describes the list of formal parameters for the function. In the example function given below, the name of the function is simple, the inputs of the functions are w, x and y with data type bit, and the type of the return data type is bit.

entity func is

port ( a : in bitvector (0 to 2);

m : out bit_vector (0 to 2));

end func;

architecture example of func is

function simple (w, x, y : bit) return bit is - function declaration

begin

return (w and x) or y; - function body

end;

being

process (a)

begin

m(0) < = simple (a(0), a(l), a(2)) ;  - function call

m(l) < = simple (a(2), a(0), a(l)); - function call

m(2) < = simple (a( 1), a(2), a(0)); - function call

end process;

end example;

• The body of the function lists the relationship between the inputs and the output to be returned. All statements in the function body are behavioural (sequential). The predefined word return is used to point of the output of the function.

• As shown in the example, the function is called by a sequential statement that should appear inside the process. When the statement, m(0) <= simple (a(0), a(l), a(2)); is called, the w takes the value of a(0). x takes the value of a(l), and y takes the value of a(2). The function returns the value of sequential statement in the function body using predefined word return and it is assigned to m(0). Similarly, other two statements are executed, and m(l) and m(2) are assigned with corresponding values.


b. Procedure

• A procedure differs from a function in that there is no return value, and the arguments of the procedure have modes (in, out, or inout). The procedure has two parts: the declaration and the body. The declaration includes the name of the procedure, the inputs to the procedure and their types, and the outputs of the procedure and their types. The syntax for a procedure body is,

procedure procedure-name (parameter list)

In the example procedure given below, the name of the procedure is simple, the inputs of the procedure are w, x and y with data type bit, and the output of the procedure is z with data type bit. In the declaration statement, procedure and is are predefined words. It is important to note that if the inputs or outputs are signals, they should be explicitly specified as follows :

procedure simple ( signal x : in bit;

signal z : out bit) is

The body of the procedure contains behavioural statements which mainly describes the relationship between the input(s) and the output(s). It is important to note that the body of the procedure cannot include the behavioural statement process.

entity proc is

port ( a : in bitvector ( 0 to 2 );

m : out bit_vector (0 to 2 ));

end proc ;

architecture example of subprograms is

procedure simple (w, x, y : in bit; z : out bit) is

- - declaration

begin

z < = (w and x) or y ; - - body of procedure

end;

begin

process (a)

begin

simple (a(0), a(l), a(2), m(0));

simple (a(2), a(0), a(l), m(l));

simple (a(l), a(2), a(0), m(2));

end process;

end example;

As shown in the example, the procedure is called by a sequential statement that should appear inside the process. When the statement simple (a(0), a(l), a(2), m(0)); is called, the w takes the value of a(0), x takes the value of a(l), y takes the value of a(2). The procedure determines the value of z by executing the sequential statement and this value is passed to m(0) after execution of the statement.

We can even pass the values having data type std_logic_vector to the procedures as follows : procedure simple_vector (x : in std_logic_vector ;

z : out std_logic_vector) is

It is important to note that, passing vectors to procedures, the length of vectors is not specified.

Review Questions

1. What is subprogram ?

2. What is procedure ? Explain with the help of example.

3. What are the types of subprograms ?

4. What is function ? Define pure and impure function.

5. Explain functions and subprograms with suitable examples.


Digital Logic Circuits: Unit V: VHDL : Tag: : Functions, Procedure, Suitable Example | VHDL - Subprograms