Synchronous Counters

Synchronous Counters

• When counter is clocked such that each flip-flop in the counter is triggered at the same time, the counter is called as synchronous counter.

1. 2- bit Synchronous Binary Up Counter

• Fig. 5.8.1 shows two stage synchronous counter.

• Clock signal is connected in parallel to clock inputs of both the flip-flops.

• The Q_A output of first stage is used to drive the J and K inputs of the second stage. 

• Initially, we assume that the Q_A = Q_B = 0.

• When positive edge of the first clock pulse is applied, flip-flop A will toggle because J_A = K_A = 1, whereas flip-flop B output will remain zero because J_B = K_B = 0.

• After first clock pulse Q_A = 1 and Q_B = 0.

• At negative going edge of the second clock pulse both flip-flops will toggle because they both have a toggle condition on their J and K inputs

(J_A = K_A = J_B = K_B = 1). Thus after second clock pulse, Q_A = 0 and Q_B = 1.

• At negative going edge of the third clock pulse flip-flop A toggles making Q_A = 1, but flip-flop B remains set i.e. Q_B = 1.

• Finally, at the leading edge of the fourth clock pulse both flip-flops toggle as their JK inputs are at logic 1. This results Q_A = Q_B = 0 and counter recycled back to its original state.

• The timing details of above operation is shown in Fig. 5.8.2.

2. 3- bit Synchronous Binary Up Counter

• Fig. 5.8.3 (a) shows 3-bit synchronous binary counter and its timing diagram.

• The state sequence for this counter is shown in Table 5.8.1.

• Looking at Fig. 5.8.3 (b), we can see that Q_A changes on each clock pulse as we progress from its original state to its final state and then back to its original state.

• Flip-flop A is held in the toggle mode by connecting J and K inputs to HIGH.

• Flip-flop B toggles, when Q_A is 1.

• When Q_A is 0, flip-flop B is in the no-change mode and remains in its present state.

• Looking at the Table 5.8.1 we can notice that flip-flop C has to change its state only when Q_B and Q_A both are at logic 1. This condition is detected by AND gate and applied to the J and K inputs of flip-flop C. Whenever both Q_A and Q_B are HIGH, the output of the AND gate makes the J and K inputs of flip-flop C HIGH and flip-flop C toggles on the following clock pulse. At all other times, the J and K inputs of flip-flop C are held LOW by the AND gate output and flip-flop does not change state.

3. 4- bit Synchronous Binary Up Counter

• Fig. 5.8.4 (a) shows logic diagram and timing diagram for 4-bit synchronous binary counter.

• As counter is implemented with negative edge triggered flip-flops, the transitions occur at the negative edge of the clock pulse.

• In this circuit, first three flip-flops work same as 3-bit counter discussed previously.

• For the fourth stage, flip-flop has to change the state when Q_A = Q_B = Q_C = 1. This condition is decoded by 3-input AND gate G₂. Therefore, when Q_A = Q_B = Q_C = 1, flip-flop D toggles and for all other times it is in no change condition.

Ex. 5.8.1 Determine f_max for the 4-bit synchronous counter if t_pd for each flip-flop is 50 ns and t_pd for each AND gate is 20 ns. Compare this with f_max for a MOD-16 ripple counter.

Sol. : For a synchronous counter the total delay that must be allowed between input clock pulses is equal to flip-flop t_pd + AND gate t_pd. Thus T_clock ≥ 50 + 20 = 70 ns and so the counter has

f_max = 1/ 70 ns = 14.3 MHz

We know that MOD-16 ripple counter used four flip-flops. With flip-flop t_pd = 50 ns, the fmax for ripple counter can be given as,

f_max(ripple)  = 1/ 4 × 50 ns = 5 MHz

4. Synchronous Down and Up/Down Counters

• A parallel/synchronous down counter can be constructed by using the inverted FF outputs to drive the following JK inputs.

• For example, the parallel up counter of Fig. 5.8.4 (a) can be converted to a down counter by connecting the  respectively. 

• The counter will then proceed through the following sequence as input pulses are applied :

• To form a parallel up/down counter the control input   is used to control whether the normal flip-flop outputs or the inverted flip-flop outputs are fed to the J and K inputs of the following flip-flops.

• A logic 1 on the  enables AND gates 1 and 2 and disables AND gates 3 and 4. This allows the QA and QB outputs through to the J and K inputs of the next flip-flops so that the counter will count up as pulses are applied.

• When   line is logic 0, AND gates 1 and 2 are disables and AND gates 3 and 4 are enabled. This allows the  outputs through to the J and K inputs of the next flip-flops so that the counter will count down as pulses are applied.

Fig. 5.8.7 shows the timing diagram for 3-bit up-down counter.

Review Questions

1. Define synchronous counter.

AU CSE Dec.-06, Marks 2

2. Explain the working of 3-bit synchronous binary up counter.

AU CSE May-08, Marks 8

3. Explain the working of synchronous up/down counter.