Two Marks Questions with Answers

Two Marks Questions with Answers

 

Q.1 What is HDL ?

Ans. : Computer Aided Design (CAD) tools are used in the design of digital systems. One such a tool is a Hardware Description Language (HDL).

 

Q.2 What are the main components of a VHDL description ?

Ans. : The main components of a VHDL description are :

1. Package (optional)

2. Entity

3. Architecture

4. Configuration(optional)

 

3. What is entity?

Ans.: Entity gives the specification of input/output signals to external circuitry. It gives interfacing between device and the other peripherals. An entity usually has one or more ports, which are analogous to the pins on a schematic symbol. All information must flow into and out of the entity through the ports. Each port must contain name, data flow direction and type.

 

Q.4 Give the syntax for VHDL entity declaration.

Ans. : The syntax of a VHDL entity declaration is as shown below :

entity entity_name is

port ( signal_names : mode signal_type;

signal_names : mode signal_type;

:

:

signal_names : mode signal_type);

end entity_name ;

 

Q.5 What is architecture ?

Ans. : Architecture specifies behavior, functionality, interconnections or relationship between inputs and outputs. It is the actual description of the design. An architecture consists of two portions : architecture declaration and architecture body.

 

Q.6 List the internal details of an entity specified by architecture body.

Ans. : An architecture body specifies the following internal details of an entity :

• As a set of concurrent assignment statements (to represent dataflow)

• As a set of interconnected components (to represent structure)

• As a set of sequential assignment statement (to represent behavior)

• As any combination of above three.

 

Q.7 Give the syntax for VHDL architecture declaration.

Ans. : The syntax for architecture is given below : architecture architecture_name of entity_name is Declarations

begin

concurrent statements;

sequential statements;

end arclutecture_name;

 

Q.8 What is the use of configuration declaration ?

Ans. : Configuration declarations may be used to associate particular design entities to component instances (unique references to lower-level components) in a hierarchical design, or to associate a particular architecture to an entity. 

 

Q.9 What is the need of package declaration ?

Ans. : There are some declarations which are common across many design units. A package is a convenient mechanism to store and share such declarations. A set of declarations contained in a package declaration may be shared by many design units. It defines items that can be made visible to other design units.

 

Q.10 How is package represented ?

Ans. : A package is represented by : 1. Package declaration 2. Package body (optional)

 

Q.11 What are the various modeling techniques in HDL ?

Ans. : There are three modelling techniques in HDL for describing a module :

1. Gate-level modeling/Structural modeling

2. Dataflow modeling

3. Behavioral modeling.

 

Q.12 What is behavioral modeling ?

Ans. : The modeling style which directly describe the behavior or the functionality of a circuit is called behavioral modeling. It is very similar in syntax and semantics to that of a high-level programming language (For example : C, Pascal). A behavioral description models the system as to how the outputs behave with the inputs.

 

Q.13 Write HDL behavioural model of D flip flop.

(Refer section 10.14.2)

 

Q.14 What is data flow modeling ?

Ans. : Data flow describes how the circuit signals flow from the inputs to the outputs. There are some concurrent statements which allow to describe the circuit in terms of operations on signals and flow of signals in the circuit. When such concurrent statements are used in a program, the style is called a dataflow modeling.

 

Q.15 What is structural modeling ?

Ans. : The modeling style which uses components or gates to model the system is called structural modeling.

 

Q.16 List the data objects supported by VHDL.

Ans. : The data objects supported by VHDL are :

1. Signals 2.Variable 3. Constants 4. File

 

Q.17 Give the classication of data types supported by VHDL.

Ans. : The VHDL data types can be broadly classified into following five data types :

1. Scalar types : The scalar types include numeric data types and enumerated data types. The numeric types consist of integer, floating point (real) and physical types. Bit, Boolean and character are all enumerated types.

2. Composite types : Array and record types are composite data types. The values of these types are collection of their elements.

3. Access types : They are pointers; they provide access to objects of a given data type.

4. File type : They provide access to object that contain a sequence of values of a given type.

5. Other types : They include the data types provided by the several external libraries.

 

Q.18 Give the comparison between signal and variable. (Refer Table 10.7.1)

 

Q.19 Give the comparison between concurrent and sequential statement.

(Refer section 10.8.4)

 

Q.20 State the use of generate statement in VHDL.

Ans. : A generate statement in VHDL is used to create repetitive structures for repetitive subdrcuits. This concept is similar to use a FOR loop. When generate statement is used, it is not necessary to write out all of the component instantiations individually.

 

Q.21 What is subprogram ?

Ans. : A subprogram defines a sequential algorithm that performs particular task. Two types of subprograms are used in VHDL : Procedures and functions. Procedures and functions in VHDL, are directly analogous to functions and procedures in a high-level programming language such as C or Pascal.

 

Q.22 How procedure differs from function ?

Ans. : A procedure differs from a function in that there is no return value, and the arguments of the procedure have modes (in, out, or inout).

 

Q.23 What do you mean by subprogram overloading ?

Ans. : It is possible to define two or more different subprograms having the same name but differing in number or type of parameters. The function is said to be overloaded in this case. The simulator or synthesizer automatically selects the correct subprogram by looking at the parameters in the call statement. Overloading is a very convenient mechanism for defining a set of functions that perform the same operation on different data types.

 

Q.24 Write HDL for half adder.

Ans. :

module half_adder (A, B, Sum, Cout);

input A;

input B;

output Sum;

output Cout;

reg Sum, Cout;

always @(A, B)

begin

#10 Sum = a ^ b ;

#10 Cout = a & b ;

end

endmodule

 

Q.25 When can RTL be used to represent digital systems ?

Ans. : When digital systems are composed of registers and combinational function blocks, the RTL can be used to represent digital systems.

 

Q.26 What is testbench ?

Ans. : Before processing a design by synthesis tool, the designer usually wants to verify that the design performs according to the specification. This is almost always done by running a simulation. Simulating a design requires generation of test data and observation of simulation results. This process is done by used of a VHDL module that is referred to as testbench.

 

Q.27 List the different type of testbenches ?

Ans. : The different type of testbenches are :

1. Stimulus only

2. Full testbench

3. Simulator specific

4. Hybrid test-bench

5. Fast testbench

 

Q.28 What is the meaning of the following RTL statement ?

T₁ : ACC ← ACC and MDR.

Ans. : The contents of register ACC are bitwised ANDed with the contents of MDR register and the result is stored in the ACC register when control signal T₁ is activated.

 

Q.29  What are the advantages of hardware languages ?

(Refer section 10.1) AU : June-14

Q.30  Write VHDL code for half adder in data flow model.  

AU : June-14

Ans. :

entity  half-add is

port   (A, B, : in bit;

sum, cout : out bit);      

end    half_add;   

architecture adder of half_add is

begin

sum < = A XOR B ;

cout < = A and B ;

end adder

 

Q.31 Write a VHDL code for 2×1 .MUX.

(Refer Listing 10.9.5)

Q.32 State the advantage of package declaration over component declaration.

(Refer section 10.2.4)

Q.33 What is the need for VHDL ?

(Refer section 10.1)

Q. 34 What are the operators present in VHDL ?

(Refer section 10.6)

Q.35 What is a package in VHDL ?

(Refer section 10.2.4)

Q. 36 Write the behavioral modeling code for a D flip flop.

(Refer section 10.14.1)

Q. 37 List out the operators present in VHDL.

(Refer section 10.6)

Q. 38 Write the behavioral model of D flip flop.

(Refer section 10.14.1)

Q. 39 What is data flow modelling in VHDL? Give its basic mechanism.

(Refer section 10.3.2)

Q. 40 Write the VHDL code to realize a 2 × 1 multiplexer.

(Refer example 10.7.4)

AU : May-16

Q. 41 Write VHDL behavioral model for D flip flop.

(Refer section 10.14.1)

AU : Dec.-16

Q.42 Give the syntax for package declaration and package body in VHDL.

(Refer sections 10.2.4 and 10.2.5)

Q.43 Write the VHDL code for 2 x 1 multiplexer using behavioral modeling.

(Refer example 10.7.3)

Q.44 What are the languages that are combined together to get VHDL language ?