Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits
University Questions with Answers (Long Answered Questions)
Analysis & Design of Synchronous Sequential Circuits | Digital Logic Circuits
Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits : University Questions with Answers (Long Answered Questions)
University Questions with Answers
(Long Answered Questions)
(Regulation
2008)
Dec.-09
Q.1
Explain in detail the operation of a 4-bit binary ripple counter. [Section 5.6]
[4]
Q.2
Design an asynchronous Modulo-8 down counter using JK flip-flops. [Section 5.6] [16]
Dec.-12
Q.3
Differentiate between analysis and design of sequential logic circuits.
[Section 5.4] [4]
(Regulation
2013)
May-15
Q.4
Design a sequence detector to detect the sequence 101 using JK flip flop.
[Section 5.10] [8]
May-16
Q.5
Design a serial adder using Mealy state model. [Section 5.4.7] [8]
Q.6
Explain the state minimization using partitioning procedure with a suitable
example. [Section 5.4.1.2] [8]
May-17
Q.7 State the differences between Moore and Melay state machines, [section 5.2.3] [2]
Digital Logic Circuits: Unit III: (b) Analysis & Design of Synchronous Sequential Circuits : Tag: : Analysis & Design of Synchronous Sequential Circuits | Digital Logic Circuits - University Questions with Answers (Long Answered Questions)
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Digital Logic Circuits
EE3302 3rd Semester EEE Dept | 2021 Regulation | 3rd Semester EEE Dept 2021 Regulation