University Questions with Answers (Long Answered Questions)

University Questions with Answers

(Long Answered Questions)

(Regulation 2008)

Dec.-10      

Q.1 Explain the design procedure of RTL using VHDL. [Section 10.19]     [10]

Q.2 Write a note on testbenches. [Section 10.21] [6]

May-11

Q.3    Describe the RTL in VHDL. [Section 10.19] [16]

Dec.-11

Q.4 Construct a VHDL module for a JK flipflop. [Section 10.14]      [8]

Q.5 Explain in detail the design procedure for register transfer language. [Section 10.19]          [16]

Q.6 Express how arithmetic and logic operations are expressed using RTL. [Section 10.19]    [8]

May-12

Q.7 Write the VHDL code for mod 6 counter.[Section 10.15]  [16]

Q.8 Explain RTL design using VHDL with the help of example. [Section 10.20] [16]

Dec.-12

Q.9 Briefly discuss the use of ’Packages’ in VHDL.[Section 10.2]     [6]

 Q.10 List and briefly explain different data types supported by VHDL. [Section 10.6]   [6]

Q.11 Write an HDL code that implements an 8:1 multiplexer. [Section 10.8]       [10]

Q.12 How is memory modelled in VHDL ? Write a VHDL code that illustrates the read and write operations of memory. [Section 10.18]        [8]

(Regulation 2013)

Dec.-14

Q.13 Explain the concept of Behavioural modeling and Structural modeling in. VHDL. Take the example of Tull Adder design for both and write the coding. [Section 10.3]         [16]

Q.14 Write a VHDL code for a 4-bit universal shift register. [Section 10.16]        [8]

Q.15 Write a VHDL code for a 4-bit universal shift register. [Section 10.17]        [8]

May-15

Q.16 Write a VHDL code to realize a full adder using.

i) Behavioral modeling [Section 10.3.1]

ii) Structural modeling [Section 10.3.3]      [16]

Dec.-15

Q.17 Write a VHDL program for full adder using structural modelling. [Section 10.3.3] [8]

Q.18 Explain in detail the RTL design procedure. [Section 10.20]    [16]

May-16

Q.19 Explain the various operators supported by VHDL. [Section 10.6.6] [8]

Q.20 Explain functions and subprograms with suitable examples. [Sections 10.10 and 10.13] [6]

Q.21 Write the VHDL code to realize a 4 - bit parallel binary adder with structural modelling and write the test bench to verify its functionality. [Sections 10.9 and 10.21] [10] 

Q.22 Write the VHDL code to realize a decade counter with behavioural modelling.

[Refer similar example in section 10.15.6] [8]

Dec.-16

Q.23 Explain in detail the concept of structural modeling in VHDL with an example of full adder. [Section 10.3.3]  [13]

Q.24 Write a short notes on built-in operators used in VHDL programming. [Section 10.6.6] [6]

Q.25 Write VHDL coding for 4 x 1 Multiplexer.

[Listing 10.8.2]    [7]

May-17

Q.26 Design a 3 - bit magnitude comparator and write the VHDL code to realize it using structural modeling. (Refer listing 10.9.8)   [13]

Q.27 Design a 4 x 4 array multiplier and write the VHDL code to realize it using structural modeling. [13]

Q.28 Write the VHDL code for the given state diagram, using behavioral modeling. [7]

Dec.-17

Q.29 Write a VHDL code to realize a full adder using behavioural modeling and structural modeling.

(Refer listing 10.3.1 and 10.9.4)        [10]

Q.30 Discuss briefly the packages in VHDL.

(Refer sections 10.2.4 and 10.2.5)     [6]

Q.31 Write an VHDL coding for realization of clocked SR flip - flop. (Refer listing 10.14.1)    [7]

Dec.-18

Q.32 Write a VHDL code to realize a half adder using behavioral modeling and structural modeling.

(Refer section 10.7.1 and Refer listing 10.9.2) [13]