VHDL

UNIT – V

Chapter – 10

VHDL

Syllabus

RTL Design - Combinational logic - Sequential circuit - Operators - Introduction to packages - Subprograms - Test bench. (Simulation /tutorial examples : Adders, Counters, Flip-Flops, Multiplexers /Demultiplexers).

Contents

10.1 Introduction to HDL …… 10-2

May-13, 14, Marks 2

10.2 Structure of VHDL Module ……. 10-2

Dec.-12, 17, May-15, 17, Marks 6

10.3 Styles of Modeling ……. 10-5

Dec.-14, 15, 16, 17, May-15, Marks 8

10.4 VHDL Identifiers and Types ……. 10-7

10.5 VHDL Data Objects ….. 10-8

10.6 VHDL Data Types and Operators …….. 10-10

Dec.-ll, 12, 15, 16, May-16, Marks 6

10.7 Structure of Behavioral Description  ……. 10-18

Dec.-10, 18, May-16, 17, Marks 16

10.8 Structure of Data Flow Description ……. 10-27

Dec.-12, 16, Marks 10

10.9 Organization of Structural Description ... 10 - 33

May-16, 17, Dec.-17,18, Marks 10

10.10 Subprograms .. 10-46

May-16, Marks 6

10.11 Declaration of Subprogram ……. 10-50

10.12 Subprogram Overloading        ……. 10-50

10.13 Examples of Procedure and Functions .... 10 - 51

May-13, 16, Marks 6

10.14 VHDL Description of Flip-Flops ….. 10-53

Dec.-11, 15, 17, May-15, Marks 8

10.15 VHDL Description for Counters ….. 10-59

May-11, 12, 16, Marks 16

10.16 VHDL Code for Registers ……. 10-66

Dec.-14, Marks 8

10.17 VHDL Description for Finite State Machines (FSM)  ….. 10-78

Dec.-14, Marks 8 

10.17 VHDL Description for Finite State Machines (FSM) ... 10 - 78

Dec.-14, Marks 8

10.18 Memory Description in VHDL .... 10 - 84

Dec.-12, Marks 8

10.19 RTL Design .... 10 - 86

Dec.-10, 11, May-11, Marks 16

10.20 RTL Design Example ... 10 - 87

May-12, Dec.-15, Marks 16

10.21 Testbenches... ... 10 - 92

Dec.-10, May-16, Marks 6

10.22 Two Marks Questions with Answers . . . . 10 - 95

10.23 University Questions with Answers

(Long Answered Questions) ….. 10 - 98