Digital Logic Circuits: Unit II: Combinational Circuits : University Questions with Answers (Long Answered Questions)
University Questions with Answers
(Long Answered Questions)
(Regulation
2008)
Dec.-10
Q.1
Define full adder. Draw logic circuit and truth table of full adder. [Section
3.11] [6]
Dec.-ll
Q.2
Write brief note on the following : DeMorgan’s theorem. [Section 3.1] [4]
Q.3
Write brief note on multiplexer. [Section 3.17] [4]
Q.4
Write brief note on binary to gray code converter. [Section 3.21] [4]
Dec.-12
Q.5
Show that a function expressed as a sum of its minterms is equivalent to a
function expressed as a product of its maxterms. [Section 3.2] [8]
Q.6
Design a 4-bit binary ripple carry adder with full adders and discuss its
operation. [Section 3.13] [8]
Dec.-13
Q.7
Draw the logic diagram of BCD - Decimal decoder and explain its operations. [Section
3.19] [16]
(Regulation
2013)
Dec.-14
Q.8
Design a full subtractor and implement it using logic gates. [Section 3.12] [8]
May-15
Q.9
Design a full adder using two half-adders and an OR gate. [Section 3.11.2] [8]
Dec.-15
Q.10
Design a full subtractor and implement using logic gates. [Section 3.12.2] [8]
May-16
Q.11
Design a full adder and implement in using suitable multiplexer. [Section
3.11.2 and example 3.17.13] [8]
Dec.-16
Q.12
Design a full subtractor and realise using logic gates. Also, implement the
same using half subtractors. [Section 3.12.2] [13]
Digital Logic Circuits: Unit II: Combinational Circuits : Tag: : Combinational Circuits | Digital Logic Circuits - University Questions with Answers (Long Answered Questions)
Digital Logic Circuits
EE3302 3rd Semester EEE Dept | 2021 Regulation | 3rd Semester EEE Dept 2021 Regulation