Types, Writing, Syntax, Advantages | VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• Before processing a design by synthesis tool, the designer usually wants to verify that the design performs according to the specification. This is almost always done by running a simulation.
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• To show how an RTL design is described in VHDL and to clarify the concepts involved, we will design a four-input adder. This design will also demonstrate how to create packages of components that can be re-used.
VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• Register Transfer Level, or RTL design lies between a purely behavioral description of the desired circuit and a purely structural one.
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• Memory is nothing but the array of registers. Each register in the array is identified by its unique address.
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
1. VHDL Code for Mealy-Type State Machines 2. VHDL Code for Moore-Type State Machines
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• In the section 10.14, we have seen the VHDL code for a D flip-flop. The n-bit register can be described in VHDL by writing a hierarchical code that includes n-instances of the D flip-flop subcircuit.
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
1. VHDL Code for a Four-bit Up Counter 2. VHDL Code for a 4-bit Up Counter using Integer Signals 3. VHDL Code for a 4-bit Down Counter 4. VHDL Code for a 3-bit Asynchronous Counter 5. VHDL Code for Asynchronous Counter with GLITCH 6. VHDL Code for Synchronous Mod-6 Counter 7. 4-bit Unsigned Up Counter with Asynchronous Load from Primary Input 8. 4-bit Unsigned Up Counter with Synchronous Load with a Constant 9. Structural Description of 3-bit Synchronous Binary Counter
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
1. Behavioral Description of D Flip-Flop using IF-THEN Statements 2. Behavioral Description of D Flip-Flop using WAIT-UNTIL Statement 3. Behavioral Description of D Flip-Flop with Asynchronous Reset/Clear 4. Behavioral Description of D Flip-Flop with Synchronous Reset/CIear 5. Behavioral Description of DFF with a Negative-Edge Clock and Asynchronous Clear 6. Behavioral Description of DFF with Positive-Edge Clock and Synchronous Set 7. Behavioral Description of DFF with Positive-Edge Clock and Clock Enable 8. Structural Description of Pulse Triggered SR Flip-Flop 9. Structural Description of Pulse Triggered D Flip-Flop 10. Structural Description of JK Flip-Flop 11. Behavioral Description of JK Flip-Flop using Case Statement 12. Description of D Flip-Flop using VHDL Function
VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
We have seen the structural description of full-adder using two half-adders. Here, we see the behavioral description of half-adder using the procedure in VHDL.
VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• It is possible to define two or more different subprograms having the same name but differing in number or type of parameters.
VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• VHDL distinguishes between a subprogram declaration and a corresponding subprogram body. The subprogram declaration contains only interface information, while the subprogram body contains :
Functions, Procedure, Suitable Example | VHDL
Subject and UNIT: Digital Logic Circuits: Unit V: VHDL
• A subprogram defines a sequential algorithm that performs particular task. Two types of subprograms are used in VHDL : Procedures and functions.