Digital Logic Circuits: Unit III: (a) Flip-Flops : University Questions with Answers (Long Answered Questions)
University Questions with Answers
(Long Answered Questions)
(Regulation
2008)
May-12
Q.1
Realize SR flip-flop using NOR gates and
explain its operation. [Section 4.2] [8]
Q.2
Convert a SR flip-flop into JK flip-flop.
[Section 4.9] [8]
Dec.-12
Q.3
Give the truth table I state table for D flip-flop. [Section 4.3] [3]
Q.4
Sketch the truth table or state table for JK flip-flop. [Section 4.4] [3]
(Regulation
2013)
Dec.-14
Q.5
Explain the various types of triggering with suitable diagrams. Compare their
merits and demerits. [Section 4.1] [8]
Q.6
Explain the circuit of a SR flip-flop and explain its operation. [Section 4.2] [8]
Dec.-15
Q.7
Realize T flip-flop using JK flip-flop. [Section 4.9] [4]
May-15
Q.8
Explain the operation of a master slave JK flip flop. [Section 4.5] [8]
May-16
Q.9
Explain the operation of a JK master slave flip flop. [Section 4.5] [8]
May-17
Q.10
Draw and explain the operation of a Master - Slave JK Flip Flop. (Refer section
4.5) [7]
Dec.-17
Q.11
Explain the operation, state diagram and characteristics of T - flip - flop and
master - slave JKflip - flop. (Refer sections 4.6 and 4.5) [13]
Q.12
Describe level triggering and edge triggering.
(Refer
section 4.1.3) [7]
Dec.-18
Q.13
Describe the design procedure with neat diagram about 4 bit bidirectional shift
register with parallel load. (Refer sections 4.6 and 4.5) [13]
Q.14
Discuss the operation of SR Latch with NOR and NAND gates analysis. (Refer
section 4.1.4) [13]
Digital Logic Circuits: Unit III: (a) Flip-Flops : Tag: : Flip-Flops | Digital Logic Circuits - University Questions with Answers (Long Answered Questions)
Digital Logic Circuits
EE3302 3rd Semester EEE Dept | 2021 Regulation | 3rd Semester EEE Dept 2021 Regulation